\doxysubsubsubsection{DMA FIFO threshold level }
\hypertarget{group___d_m_a___f_i_f_o__threshold__level}{}\label{group___d_m_a___f_i_f_o__threshold__level}\index{DMA FIFO threshold level@{DMA FIFO threshold level}}


DMA FIFO level.  


\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___d_m_a___f_i_f_o__threshold__level_ga4debbd5733190b61b2115613d4b3658b}{DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+1\+QUARTERFULL}}~((uint32\+\_\+t)0x00000000U)
\item 
\#define \mbox{\hyperlink{group___d_m_a___f_i_f_o__threshold__level_gad2b071aa3a3bfc936017f12fb956c56f}{DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+\+HALFFULL}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga63716e11d34bca95927671055aa63fe8}{DMA\+\_\+\+Sx\+FCR\+\_\+\+FTH\+\_\+0}})
\item 
\#define \mbox{\hyperlink{group___d_m_a___f_i_f_o__threshold__level_gae1e4ba12bae8440421e6672795d71223}{DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+3\+QUARTERSFULL}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3d780fc1222a183071c73e62a0524a1}{DMA\+\_\+\+Sx\+FCR\+\_\+\+FTH\+\_\+1}})
\item 
\#define \mbox{\hyperlink{group___d_m_a___f_i_f_o__threshold__level_ga5de463bb24dc12fe7bbb300e1e4493f7}{DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+\+FULL}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44c16978164026a81f5b07280e800e7f}{DMA\+\_\+\+Sx\+FCR\+\_\+\+FTH}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
DMA FIFO level. 



\label{doc-define-members}
\Hypertarget{group___d_m_a___f_i_f_o__threshold__level_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___d_m_a___f_i_f_o__threshold__level_ga4debbd5733190b61b2115613d4b3658b}\index{DMA FIFO threshold level@{DMA FIFO threshold level}!DMA\_FIFO\_THRESHOLD\_1QUARTERFULL@{DMA\_FIFO\_THRESHOLD\_1QUARTERFULL}}
\index{DMA\_FIFO\_THRESHOLD\_1QUARTERFULL@{DMA\_FIFO\_THRESHOLD\_1QUARTERFULL}!DMA FIFO threshold level@{DMA FIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_FIFO\_THRESHOLD\_1QUARTERFULL}{DMA\_FIFO\_THRESHOLD\_1QUARTERFULL}}
{\footnotesize\ttfamily \label{group___d_m_a___f_i_f_o__threshold__level_ga4debbd5733190b61b2115613d4b3658b} 
\#define DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+1\+QUARTERFULL~((uint32\+\_\+t)0x00000000U)}

FIFO threshold 1 quart full configuration \Hypertarget{group___d_m_a___f_i_f_o__threshold__level_gae1e4ba12bae8440421e6672795d71223}\index{DMA FIFO threshold level@{DMA FIFO threshold level}!DMA\_FIFO\_THRESHOLD\_3QUARTERSFULL@{DMA\_FIFO\_THRESHOLD\_3QUARTERSFULL}}
\index{DMA\_FIFO\_THRESHOLD\_3QUARTERSFULL@{DMA\_FIFO\_THRESHOLD\_3QUARTERSFULL}!DMA FIFO threshold level@{DMA FIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_FIFO\_THRESHOLD\_3QUARTERSFULL}{DMA\_FIFO\_THRESHOLD\_3QUARTERSFULL}}
{\footnotesize\ttfamily \label{group___d_m_a___f_i_f_o__threshold__level_gae1e4ba12bae8440421e6672795d71223} 
\#define DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+3\+QUARTERSFULL~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3d780fc1222a183071c73e62a0524a1}{DMA\+\_\+\+Sx\+FCR\+\_\+\+FTH\+\_\+1}})}

FIFO threshold 3 quarts full configuration \Hypertarget{group___d_m_a___f_i_f_o__threshold__level_ga5de463bb24dc12fe7bbb300e1e4493f7}\index{DMA FIFO threshold level@{DMA FIFO threshold level}!DMA\_FIFO\_THRESHOLD\_FULL@{DMA\_FIFO\_THRESHOLD\_FULL}}
\index{DMA\_FIFO\_THRESHOLD\_FULL@{DMA\_FIFO\_THRESHOLD\_FULL}!DMA FIFO threshold level@{DMA FIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_FIFO\_THRESHOLD\_FULL}{DMA\_FIFO\_THRESHOLD\_FULL}}
{\footnotesize\ttfamily \label{group___d_m_a___f_i_f_o__threshold__level_ga5de463bb24dc12fe7bbb300e1e4493f7} 
\#define DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+\+FULL~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44c16978164026a81f5b07280e800e7f}{DMA\+\_\+\+Sx\+FCR\+\_\+\+FTH}})}

FIFO threshold full configuration \Hypertarget{group___d_m_a___f_i_f_o__threshold__level_gad2b071aa3a3bfc936017f12fb956c56f}\index{DMA FIFO threshold level@{DMA FIFO threshold level}!DMA\_FIFO\_THRESHOLD\_HALFFULL@{DMA\_FIFO\_THRESHOLD\_HALFFULL}}
\index{DMA\_FIFO\_THRESHOLD\_HALFFULL@{DMA\_FIFO\_THRESHOLD\_HALFFULL}!DMA FIFO threshold level@{DMA FIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_FIFO\_THRESHOLD\_HALFFULL}{DMA\_FIFO\_THRESHOLD\_HALFFULL}}
{\footnotesize\ttfamily \label{group___d_m_a___f_i_f_o__threshold__level_gad2b071aa3a3bfc936017f12fb956c56f} 
\#define DMA\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+\+HALFFULL~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga63716e11d34bca95927671055aa63fe8}{DMA\+\_\+\+Sx\+FCR\+\_\+\+FTH\+\_\+0}})}

FIFO threshold half full configuration 